Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology

A new transistor architecture is developed by reusing already existing fabrication process bricks in an embedded non-volatile memory (eNVM) sub-40 nm CMOS technology, resulting a middle-voltage zero-cost transistor, ideal for low-cost products. TCAD simulations are undertaken to confirm the feasibility of optimization and predict performance reliability. The fabricated then electrically characterized. device shows good analogue performances no cost added. hot-carrier injection (HCI) degradation evaluation performed confirms reliability device.